A high bandwidth memory (HBM) is being developed as a next-generation graphic memory for substituting double data rate 5 (DDR5) synchronous dynamic random access memory (SDRAM), wide input-output memory, etc. The HBM may provide multiple-input shift register or multiple-input signature register (MISR) function to test and train a communication link between the HBM and a host device. For the MISR function, the HBM may include a shift register circuit having multiple input terminals with a feedback loop. The shift register circuit may receive and compress input data from the host device to generate a signature, that is, test result data. The signature may be returned to the host device to compare the signature with a predicted value stored in the host device. When there is a mismatch between the signature and the predicted value, the host device may resend the input data with a modified timing condition to find a correct transmission condition, or the host may replace the faulty link with a redundant link.
Although a MISR circuit may not require registers to store all of the input data, additional circuits for the MISR function may cause design overheads for the HBM. Furthermore, if a setup/hold margin for a test operation has to be adjusted independently from a setup/hold margin for a normal access operation, the design burden may be increased significantly.